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TS3A5017 데이터시트(PDF) 5 Page - Texas Instruments |
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5 / 20 page TS3A5017 14 W DUAL SP4T ANALOG SWITCH 3.3V/2.5V DUAL 4:1 ANALOG MULTIPLEXER/DEMULTIPLEXER SCDS188 – JANUARY 2005 www.ti.com 5 Electrical Characteristics for 2.5-V Supply(1) V+ = 2.3 V to 2.7 V, TA = −40°C to 85°C (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS TA V+ MIN TYP MAX UNIT Analog Switch Analog signal range VD, VS 0 V+ V ON-state ron 0 ≤ VS ≤ V+, Switch ON, 25 °C 2.3 V 20.5 22 Ω ON-state resistance ron 0 ≤ VS ≤ V+, ID = −24 mA, Switch ON, See Figure 13 Full 2.3 V 24 Ω ON-state resistance match ∆ron VS = 1.6 V, Switch ON, 25 °C 2.3 V 1 2 Ω resistance match between channels ∆ron VS = 1.6 V, ID = −24 mA, Switch ON, See Figure 13 Full 2.3 V 3 Ω ON-state resistance ron(flat) 0 ≤ VS ≤ V+, Switch ON, 25 °C 2.3 V 16 18 Ω resistance flatness ron(flat) 0 ≤ VS ≤ V+, ID = −24 mA, Switch ON, See Figure 13 Full 2.3 V 20 Ω S IS(OFF) VS = 0.5 V, VD = 2.2 V, or Switch OFF, 25 °C 2.7 V −0.1 0.05 0.1 S OFF leakage IS(OFF) SD or VS = 2.2 V, VD = 0.5 V, Switch OFF, See Figure 14 Full 2.7 V −0.2 0.2 µA OFF leakage current ISPWR(OFF) VS = 0 to 3.6 V, Switch OFF, 25 °C 0 V −1 0.5 1 µA current ISPWR(OFF) VS = 0 to 3.6 V, VD = 3.6 V to 0, Switch OFF, See Figure 14 Full 0 V −5 5 D ID(OFF) VD = 0.5 V, VS = 2.2 V, or Switch OFF, 25 °C 2.7 V −0.1 0.05 0.1 D OFF leakage ID(OFF) DS or VD = 2.2 V, VS = 0.5 V, Switch OFF, See Figure 14 Full 2.7 V −0.2 0.2 µA OFF leakage current IDPWR(OFF) VD = 0 to 5.5 V, Switch OFF, 25 °C 0 V −1 0.5 1 µA current IDPWR(OFF) VD = 0 to 5.5 V, VS = 5.5 V to 0, Switch OFF, See Figure 14 Full 0 V −5 5 S ON leakage IS(ON) VS = 0.5 V, VD = Open, or Switch ON, 25 °C 2.7 V −0.1 0.05 0.1 A ON leakage current IS(ON) SD or VS = 2.2 V, VD = Open, Switch ON, See Figure 15 Full 2.7 V −0.2 0.2 µA D ON leakage ID(ON) VD = 0.5 V, VS = Open, or Switch ON, 25 °C 2.7 V −0.1 0.05 0.1 A ON leakage current ID(ON) DS or VD = 2.2 V, VS = Open, Switch ON, See Figure 15 Full 2.7 V −0.2 0.2 µA Digital Control Inputs (IN1, IN2)(2) Input logic high VIH Full 1.7 5.5 V Input logic low VIL Full 0 0.7 V Input leakage IIH, IIL VI = 5.5 V or 0 25 °C 2.7 V −1 0.05 1 A Input leakage current IIH, IIL VI = 5.5 V or 0 Full 2.7 V −1 1 µA (1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. |
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