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CD54HC08 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Texas Instruments

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๋ถ€ํ’ˆ๋ช… CD54HC08
์ƒ์„ธ๋‚ด์šฉ  High-Speed CMOS Logic Quad 2-Input AND Gate
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CD54HC08 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Texas Instruments

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6
Transition Times (Figure 1)
tTLH, tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
37
-
----
pF
HCT TYPES
Propagation Delay, Input to
Output Y (Figure 2)
tPLH, tPHL CL = 50pF
4.5
-
-
25
-
31
-
38
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL CL = 15pF
5
-
10
-
----
ns
Transition Times (Figure 2)
tTLH, tTHL CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
CI
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
5
-
51
-
----
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC
2 f
i (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Switching Speci๏ฌcations Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%


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