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HDMP-1032 데이터시트(HTML) 6 Page - Agilent(Hewlett-Packard)

부품명 HDMP-1032
상세내용  1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
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제조사  HP [Agilent(Hewlett-Packard)]
홈페이지  http://www.home.agilent.com
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HDMP-1032 데이터시트(HTML) 6 Page - Agilent(Hewlett-Packard)

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Sign
The sign circuitry determines the
disparity of the encoded word.
Disparity is defined as the total
number of high bits minus the
total number of low bits.
Accumulator Block
This block is responsible for
keeping track of total disparity
of all previously sent words.
Invert Block
The Invert block is responsible
for maintaining the DC balance
of the serial line. It determines
based on history and the sign
of the current encoded word
whether the current encoded
word should be inverted to
bring the serial line closer to
the desired 50% duty cycle.
HDMP-1034 Rx Block Diagram
The HDMP-1034 receiver was
designed to convert a serial data
signal sent from the HDMP-1032
into either 16 or 17 bit wide
parallel data. The HDMP-1034
performs the following functions:
• Frequency Lock
• Phase Lock
• Encoded Word Synchronization
• De-multiplexing
• Word Decoding
• Encoding Error Detection
Input Sampler and Clock-Data
Recovery (CDR)
In order to compensate for any
amplitude distortion present in
the serial data signal, the high-
speed inputs, HSIN
± , are always
equalized. The CDR block locks
to the frequency of the REFCLK
and to the phase of the sampled
input signal. The recovered
data is sent to the DEMUX block
and a bit-rate clock is sent to
the Clock Generator block. If
the serial data signal is absent,
the CDR block will maintain
frequency lock onto REFCLK.
Figure 4. HDMP-1034 Receiver Block Diagram.
The RXDIV1/0 pins select the
data rate range by dividing the
VCO range by 1, 2 or 4. When
RXDIV1/0 = 1/1, the internal
VCO is bypassed and the test
clock input TSTCLK can be
used as the serial input.
Clock Generator
Using the recovered bit-rate
clock, the CLOCK GENERATOR
block generates all of the re-
quired internal clocks including
the word rate clocks: RXCLK0/1.
Using the WORD ALIGN block’s
bit adjust output, the phase of
the word-rate clocks is adjusted
bit by bit for proper word align-
ment. For testing purposes
this adjustment function can be
disabled using the WSYNCDSB
input; word alignment can also
be forced using the #RESET pin.
RXREADY
WORD
ALIGN
SYNC
LOGIC
RXERROR
RXDATA
RXCNTL
SHFOUT
SRQOUT
RXDSLIP
RXFLAG
RX[0-15]
SHFIN
SRQIN
PASSENB
INVERT
DECODE
FLAG
DESCRM
HSIN
CLOCK
GENERATOR
DEMUX
CDR
RXCLK0/1
REFCLK
PASS SYSTEM
RXCAP1/0
+


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