전자부품 데이터시트 검색엔진 |
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KMPC870 데이터시트(PDF) 69 Page - Freescale Semiconductor, Inc |
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KMPC870 데이터시트(HTML) 69 Page - Freescale Semiconductor, Inc |
69 / 92 page MPC885/MPC880 Hardware Specifications, Rev. 3 69 Freescale Semiconductor UTOPIA AC Electrical Specifications Figure 69 shows the I2C bus timing. Figure 69. I2C Bus Timing Diagram 13 UTOPIA AC Electrical Specifications Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface. Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (internal clock option) Output 4 ns ns Duty cycle 50 50 % Frequency 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (and PHREQ and PHSEL active delay in multi-PHY mode) Output 2 ns 16 ns ns U3 UTPB, SOC, Rxclav and Txclav setup time Input 4 ns ns U4 UTPB, SOC, Rxclav and Txclav hold time Input 1 ns ns Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (Internal clock option) Output 4 ns ns Duty cycle 50 50 % Frequency 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active delay (PHREQ and PHSEL active delay in multi-PHY mode) Output 2 ns 16 ns ns U3 UTPB_Aux, SOC_Aux, Rxclav and Txclav setup time Input 4 ns ns U4 UTPB_Aux, SOC_Aux, Rxclav and Txclav hold time Input 1 ns ns SCL 202 205 203 207 204 208 206 209 211 210 SDA |
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