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GS82032AQ-133I 데이터시트(PDF) 7 Page - GSI Technology

부품명 GS82032AQ-133I
상세설명  64K x 32 2M Synchronous Burst SRAM
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
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Rev: 1.09 7/2002
7/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82032AT/Q-180/166/133/100
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
WR
R
WR
X
X
X
CR
R
CW
CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.


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