전자부품 데이터시트 검색엔진 |
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CS5335-KS 데이터시트(PDF) 11 Page - Cirrus Logic |
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CS5335-KS 데이터시트(HTML) 11 Page - Cirrus Logic |
11 / 20 page P7 - Overrange 0 - Analog input less than full-scale level 1 - Analog input greater than full-scale P6 - Idle channel 0 - Analog input >-60 dB from full-scale 1 - Analog input <-60 dB from full-scale P5 to P0 - Peak Signal Level Bits (1 dB steps) Inputs <0 dB P5 - P0 0 dB 000000 -1 dB 000001 -2 dB 000010 -60 dB 111100 Inputs >0 dB P5 - P0 0 dB 000000 +1 dB 000001 +2 dB 000010 +3 dB 000011 Bar Graph Mode This mode provides a decoded output format which indicates the peak Peak Signal Level in a "Bar Graph" format. Input Level P7 - P0 Overflow 11111111 0 dB to -3 dB 01111111 -3 dB to -6 dB 00111111 -6 dB to -10 dB 00011111 -10 dB to -20 dB 00001111 -20 dB to -30 dB 00000111 -30 dB to -40 dB 00000011 -40 dB to -60 dB 00000001 < - 60 dB 00000000 Overflow Overflow indicates analog input overrange, for both the Left and Right channels, since the last update request on the Peak Update pin. A value of 1 indicates an overrange condition. The left channel information is output on OVFL during the left channel portion of LRCK. The right channel information is available on OVFL during the right channel portion of LRCK. Initialization Upon initial power-up, the digital filters and delta-sigma modulators are reset and the internal voltage reference is powered down. The CS5334/5 will remain in the power-down mode until valid clocks are presented. A valid MCLK is required to exit power-down in Master Mode. However, in Slave Mode, MCLK and LRCK of the proper ratio are required to exit power-down. MCLK occurrences are also counted over one LRCK period to determine the MCLK / LRCK frequency ratio in Slave Mode. Power is then ap- plied to the internal voltage reference, the analog inputs will move to approximately 2.2V and out- put clocks will begin (Master Mode only). This process requires 32 periods of LRCK and is fol- lowed by the initialization sequence. Initialization with High Pass Filter Enabled 28,672 LRCK cycles are required for the initiali- zation sequence with the high pass filter enabled. This time is dominated by the settling time re- quired for the high pass filter. Initialization and Internal Calibration with High Pass Filter Disabled If the HP DEFEAT pin is high (high pass filter disabled) during the initialization sequence, the CS5334/5 will perform an internal dc calibration by: 1. disconnecting the internal ADC inputs from the input pins, 2. connecting the (differential) ADC inputs to a common reference voltage, CS5334 CS5335 DS237PP2 11 |
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