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KM736V687A 데이터시트(PDF) 2 Page - Samsung semiconductor |
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KM736V687A 데이터시트(HTML) 2 Page - Samsung semiconductor |
2 / 16 page KM736V687A 64Kx36 Synchronous SRAM - 2 - Rev 3.0 December 1998 WEc WEd FAST ACCESS TIMES PARAMETER Symbol -7 -8 -9 Unit Cycle Time tCYC 8.5 10 12 ns Clock Access Time tCD 7.5 8 9 ns Output Enable Access Time tOE 3.5 3.5 3.5 ns 64Kx36-Bit Synchronous Burst SRAM The KM736V687A is 2,359,296 bits Synchronous Static Ran- dom Access Memory designed to support zero wait state per- formance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 64K words of 36 bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high perfor- mance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status pro- cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system ′s burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The KM736V687A is implemented with SAMSUNG ′s high per- formance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to mini- mize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • Synchronous Operation. • On-Chip Address Counter. • Write Self-Timed Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention. • TTL-Level Three-State Output. • 100-TQFP-1420A CLK LBO ADV ADSC ADSP CS1 CS2 CS2 GW BW WEa WEb OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd BURST CONTROL LOGIC BURST 64Kx36 ADDRESS CONTROL OUTPUT DATA-IN ADDRESS COUNTER MEMORY ARRAY REGISTER REGISTER BUFFER LOGIC A ′0~A′1 A0~A1 A2~A15 A0~A15 |
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