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TC9205M 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers

부품명 TC9205M
상세설명  5-Port 10/100/1000 Smart Ethernet Switch
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TC9205M
Preliminary Data Sheet
Pin Listing (continued)
No.
Pin label
Type
Description
P17 Vdd 3.3
P
Digital +3.3V power supply for I/O
T2
TxEr1
I/Opd Transmit Error
N2
TxClk1
I
MII transmit clock
J2
Crs1
Is
MII carrier sense indication
J3
Col1
Is
MII collision indication
N1
RxEr1
Is
Receive Error
L17
Vss 3.3
G
Digital ground for I/O
M2
RxClk1
I
MII receive clock
M1
RxDv1
Is
GMII/MII data valid
J1
RxData1_0
Is
GMII receive data - least significant nibble.
MII receive data
K3
RxData1_1
Is
GMII receive data - least significant nibble.
MII receive data
K2
RxData1_2
Is
GMII receive data - least significant nibble.
MII receive data
M17 Vdd 3.3
P
Digital +3.3V power supply for I/O
K1
RxData1_3
Is
GMII receive data - least significant nibble.
MII receive data
L4
RxData1_4
Is
GMII receive data - most significant nibble
L3
RxData1_5
Is
GMII receive data - most significant nibble
L2
RxData1_6
Is
GMII receive data - most significant nibble
L1
RxData1_7
Is
GMII receive data - most significant nibble
U4
selsck
Is
Selects the source for the system clock.
selsck - ‘1’ - sysck is driven by a 25MHz external clock.
U1
gtxck
I
The 125Mhz reference clock for 1000Mbps operating mode. This
clock is used as a reference clock for the GMII transmission clock for
every port.
V1
Vdd 2.0
P
Digital +2.0V power supply for core
V2
BcstLED
I/Opd The led can signal filtering of broadcast frames Also the led remains
lit if the POST test fails, which indicates a faulty chip.
V3
OvUnLED
O
The led is lit whenever a unicast packets overflow condition is
reached and some frames are dropped by the buffer management
engine.
D9
Vss 2.0
G
Digital ground for core
U3
sysck
I
The 25MHz system clock.
U2
reset
Ipus
General reset.
W9
TxData2_7
I/Opd GMII transmit data - most significant bit
Y9
TxData2_6
I/Opd GMII transmit data - bit 6
Y8
TxData2_5
I/Opd GMII transmit data - bit 5
W8
TxData2_4
I/Opd GMII transmit data - bit 4
TxData2_3
GMII/MII transmit data - bit 3
V8
PriBndw1
I/Opd
Priority bandwidth configuration pins.
PriBndw(1)is latched on reset
N17 Vdd 2.0
P
Digital +2.0V power supply for core
Confidential.
8/51
July 30, 2003
Copyright © 2003, IC Plus Corp.
TC9205M-DS-R03


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