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CDC305 데이터시트(PDF) 1 Page - Texas Instruments |
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CDC305 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 7 page CDC305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Replaces SN74AS305 D Maximum Output Skew of 1 ns D Maximum Pulse Skew of 1ns D TTL-Compatible Inputs and Outputs D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D Package Options Include Plastic Small-Outline (D) Package and Standard Plastic (N) 300-mil DIPs description The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input. The CDC305 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver when a divide-by-two function is required. The CDC305 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE INPUTS OUTPUTS CLR PRE CLK Q1– Q4 Q5– Q8 L H X L H H LX H L L LX L† L† H HL Q0 Q0 H H ↑ Q0 Q0 † This configuration does not persist when PRE or CLR returns to its inactive (high) level. Copyright © 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q3 Q4 GND GND GND Q5 Q6 Q7 Q2 Q1 CLR VCC VCC CLK PRE Q8 D OR N PACKAGE (TOP VIEW) |
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