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M390S2858DT1 데이터시트(PDF) 11 Page - Samsung semiconductor

부품명 M390S2858DT1
상세설명  128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
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제조업체  SAMSUNG [Samsung semiconductor]
홈페이지  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

M390S2858DT1 데이터시트(HTML) 11 Page - Samsung semiconductor

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REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
Byte #
Function described
Function Supported
Hex value
Note
-7C
-7A
-7C
-7A
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
11
0Bh
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
75h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
54h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
7.8us, support self refresh
82h
13
Primary SDRAM width
x4
04h
14
Error checking SDRAM width
x4
04h
15
Minimum clock delay for back-to-back random column address
tCCD = 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
address & control inputs and
On-card PLL
1Fh
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
75h
A0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
54h
60h
2
25
SDRAM cycle time @CAS latency of 1
-
-
00h
00h
2
26
SDRAM access time @CAS latency of 1
-
-
00h
00h
2
27
Minimum row precharge time (=tRP)
15ns
20ns
0Fh
14h
28
Minimum row active to row active delay (tRRD)
15ns
15ns
0Fh
0Fh
29
Minimum RAS to CAS delay (=tRCD)
15ns
20ns
0Fh
14h
30
Minimum activate precharge time (=tRAS)
45ns
45ns
2Dh
2Dh
31
Module Row density
2 Rows of 512MB
80h
32
Command and Address signal input setup time
1.5ns
15h
33
Command and Address signal input hold time
0.8ns
08h
34
Data signal input setup time
1.5ns
15h
M390S2858DT1-C7A/C7C
•Organization : 128MX72
•Composition : 128MX4 * 18ea
•Used component part # : K4S510632D-TC75/C7C
•# of banks in module : 2 Rows
•# of banks in component : 4 banks
•Feature : 1,700 mil height & double sided
•Refresh : 8K/64ms
•Contents :


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