Everest Semiconductor

ES7144LV

Rev 5.0

December, 2010

3

3. APPLICATION DESCRIPTIONS

Sampling Rate and Input Clocks

The serial audio input data is transmitted to the device at SDATA pin. According to the

sampling rate, the device can work in three speed modes, single speed, double

speed and quad speed. The device can detect the speed mode of the input data

stream automatically when the sampling rate falls into the auto detection ranges

listed in Table1. If the sampling rate is outside the auto detection ranges, the device

will not work properly.

MODE

Fs Auto Detection Range

CLKIN/LRCK Ratio

Single Speed

8kHz – 50kHz

256, 384, 512, 768, 1024

Double Speed

84kHz – 100kHz

128, 192, 256, 384, 512

Quad Speed

167kHz – 200kHz

128, 192, 256

The device works with the input system clock CLKIN, sample data clock LRCK and

bit clock SCLK. The data clock and bit clock must be synchronously derived from the

system clock with some specific rates. The device only supports the CLKIN/LRCK

ratios listed in Table1. The LRCK/SCLK ratio is normally 64. The device detects clock

ratios automatically, and it will not work properly if any ratio is incorrect.

Audio Data Input

The ES7144LV can accept I²S serial audio input data from 16-bit to 24-bit. The

device can detect the data word length automatically. The relationship of SDATA,

SCLK and LRCK for the format is illustrated through Figures 2.

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

LEFT CHANNEL

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

RIGHT CHANNEL

SDATA

SCLK

LRCK

Power Up and Power Down

Upon applying VDD, the device will reset itself and enter power down state. During

this state, the device clamps outputs to ground and power down the device operation

except for clock management unit. Once proper CLKIN and LRCK clocks are applied,

the device will leave power down state, and the device outputs ramp from ground to

Table 1 Auto Detection Ranges and CLKIN/LRCK Ratio

Figure 2 I²S serial audio data format up to 24-bit