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PC133 Clock Generator for SiS630/Pentium
®III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07035 Rev. **
05/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 1 of 18
http://www.cypress.com
APPROVED PRODUCT
C9630
Product Features
•
Supports Pentium
III, K6, and Socket 7 CPU’s
•
Designed to SiS630 & SiS540 Chipset requirements
•
3 copies of CPU Clock (CPU[0:2] )
•
14 copies of SDRAM Clock (SDRAM[0:13]
•
7 copies of PCI Clock
•
2 REF(0:1) Clock outputs
•
1 USB Clock (Non SSC), 48MHz
•
1 programmable SIO (Non SSC), 24/48MHz
•
133 MHz SDRAM support
•
Cypress Spread Spectrum for best EMI reduction
•
SMBus Support with read back capabilities.
•
Dial-a-Frequency™ Feature
•
48 Pin SSOP package.
Block Diagram
Fig.1
Frequency Table (MHz)
FS3
FS2
FS1
FS0
CPU
SDRAM
PCICLK
0
0
0
0
66.6
100.0
33.3
0
0
0
1
100.0
100.0
33.3
0
0
1
0
150.0
100.0
37.5
0
0
1
1
133.3
100.0
33.3
0
1
0
0
66.8
133.6
33.4
0
1
0
1
100.0
133.3
33.3
0
1
1
0
100.0
150.0
37.5
0
1
1
1
133.3
133.3
33.3
1
0
0
0
66.9
66.9
33.4
1
0
0
1
97.2
97.2
32.4
1
0
1
0
70.0
105.0
35.0
1
0
1
1
95.0
95.0
31.6
1
1
0
0
95.0
126.7
31.6
1
1
0
1
112.0
112.0
37.3
1
1
1
0
97.0
129.3
32.4
1
1
1
1
96.0
96.0
32.0
Table 1
Note: *Programmable to 48 MHz via SMBus
Pin Configuration
Fig.2
VDD
VDD
VDDcpu
VDD
VDD
VDD
VDD
VDD
VDD
Xin
Xout
REF1
REF0/S3
CPU(0:2)
SDRAM(0:13)
PCI(2:6)
PCI0/S1
PCI1/S2
48MHz/S0
24_48MHz
DATA
SCLK
PLL1
Rin
s1
s0
sdata
sclk
cpu
sdram
pci
s3
s2
PLL2
Rin
48
i2c-clk
i2c-data
24 or 48
1
1
30pF
300K
30pF
3
14
5
1
1
1
1
VDD
S3 / REF0
VSS
XIN
XOUT
VDD
S1/ PCI0
S2 / PCI1
PCI2
VSS
PCI3
PCI4
PCI5
PCI6
VDD
VSS
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
VSS
SDATA
SCLK
REF1
VDDC
CPU0
CPU1
VSS
CPU2
VDD
SDRAM13
SDRAM12
VSS
SDRAM11
SDRAM10
VDD
SDRAM9
SDRAM8
VSS
SDRAM7
SDRAM6
VDD
SDRAM5
SDRAM4
VDD
S0 / 48MHz
24_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25