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S-812C31BPI-C4LTFU ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - ABLIC Inc.

๋ถ€ํ’ˆ๋ช… S-812C31BPI-C4LTFU
์ƒ์„ธ๋‚ด์šฉ  16 V INPUT, 75 mA VOLTAGE REGULATOR
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์ œ์กฐ์‚ฌ  ABLIC [ABLIC Inc.]
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S-812C31BPI-C4LTFU ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 24 Page - ABLIC Inc.

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16 V INPUT, 75 mA VOLTAGE REGULATOR
S-812C Series
Rev.7.0_01
24
๏ฎ
Precautions
๏‚ท Wiring patterns for the VIN pin, the VOUT pin and GND should be designed so that the impedance is low.
When mounting an output capacitor between the VOUT pin and the VSS pin (CL) and a capacitor for
stabilizing the input between the VIN pin and the VSS pin (CIN), the distance from the capacitors to these
pins should be as short as possible.
๏‚ท Note that generally the output voltage may increase when a series regulator is used at low load current
(1
๏ญA or less).
๏‚ท At low load current (100 ๏ญA or less) output voltage may increase when the regulating operation is halted
by the ON/OFF pin.
๏‚ท Generally a series regulator may cause oscillation, depending on the selection of external parts. The
following conditions are recommended for the S-812C Series. However, be sure to perform sufficient
evaluation under the actual usage conditions for selection, including evaluation of temperature
characteristics.
Equivalent Series Resistance (ESR): 10
๏— or less (in case of using output capacitor)
Input series resistance (RIN):
10
๏— or less
๏‚ท The voltage regulator may oscillate when the impedance of the power supply is high and the input
capacitance is small or an input capacitor is not connected.
๏‚ท Overshoot may occur in the output voltage momentarily if the voltage is rapidly raised at power-on or when
the power supply fluctuates. Sufficiently evaluate the output voltage at power-on with the actual device.
๏‚ท The application conditions for the input voltage, the output voltage, and the load current should not exceed
the package power dissipation.
๏‚ท Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
๏‚ท ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
๏ฎ
Precautions for WLP package
โ— The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower
strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of the
handing of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, and
needs to be kept out of contact with the external potential.
โ— In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it
may affect the characteristic of a device when exposed a device in the bottom of a high light source.


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