TMP86FM29

2004-03-01

Difference

Comparison table of TMP86C829B/H29B/M29B/PM29A/PM29B/C929AXB and TMP86FM29

TMP86C829B

TMP86CH29B

TMP86CM29B

TMP86PM29A

TMP86PM29B

TMP86C929AXB

(Emulation chip)

(Note 3)

TMP86FM29F

ROM

8 K (Mask ROM)

16 K (Mask ROM)

32 K (Mask ROM)

32 K (OTP)

−

32 K (Flash)

RAM

512

1.5 K

1.5 K

1.5 K

−

2 K

I/O

42 pin

42 pin (MCU part)

42 pin

External

Interrupt

5 pin

5 pin

AD Converter

10-bit AD converter

× 8 ch

10-bit AD converter

× 8 ch

Timer Counter

18-bit timer

× 1 ch

8-bit timer

× 4 ch

18-bit timer

× 1 ch

8-bit timer

× 4 ch

Serial Interface

8-bit UART / SIO

× 1 ch

8-bit UART / SIO

× 1 ch

LCD

32 seg

× 4 com

32 seg

× 4 com (Note 2)

Key-on

Wakeup

4 ch

4 ch

Operating

Voltage

in MCU Mode

1.8 to 5.5 V at 4.2 MHz

2.7 to 5.5 V at 8 MHz

4.5 to 5.5 V at 16 MHz

1.8 to 5.25 V at 4.2 MHz

2.7 to 5.25 V at 8 MHz

4.5 to 5.25 V at 16 MHz

1.8 to 3.6 V at 4.2 MHz (External clock)

1.8 to 3.6 V at 8 MHz (Resonator)

2.7 to 3.6 V at 16 MHz

Operating

Temperature

in MCU Mode

−40 to 85℃

0 to 60°C

−40 to 85°C

Writing to

Flash Memory

−

2.7 to 3.6V at 16 MHz

25°C

± 5°C

CPU Wait (Note 1)

N/A

Available

Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait

period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions

are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set.

In this case, if the IMF has been set to “1”, the interrupt service routine is executed after CPU wait

period. For details refer to 2.14 “Flash Memory” in TMP86FM29 data sheet.

Thus, even if the same software is executed in 86FM29 and 86C829B/H29B/M29B/PM29A/PM29B

/C929AXB, the operation process is not the same. Therefore, when the final operating confirmation

on target application is executed for software development of Mask ROM Product

(86C829B/H29B/M29B), not the Flash product (86FM29) but the OTP product (86PM29A/PM29B)

should be used.

Halt/Operate

Condition

Wait Time

CPU

Peripherals

After reset release

2

10

/fc[s]

Halt

Halt

Changing from STOP mode to NORMAL mode

(at EEPCR<MNPWDW>

= “1”)

2

10

/fc[s]

Halt

Operate

Changing from STOP mode to SLOW mode

(at EEPCR<MNPWDW>

= “1”)

2

3

/fs[s]

Halt

Operate

Changing from IDLE0/1/2 mode to NORMAL mode

(at EEPCR<ATPWDW>

= “0”)

2

10

/fc[s]

Halt

Operate

Changing from SLEEP0/1/2 mode to SLOW mode

(at EEPCR<ATPWDW>

= “0”)

2

3

/fs[s]

Halt

Operate