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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TWR-LS1021A 데이터시트(PDF) 24 Page - Freescale Semiconductor, Inc |
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TWR-LS1021A 데이터시트(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 71 page  Architecture TWR-LS1021A Reference Manual, Rev. 0 Freescale Semiconductor 2-9 2.6.1.1 Single-Source SYSCLK A new feature supported on TWR-LS1021A is “single-source” clocking. In this mode, a differential clock is supplied to the DIFF_SYSCLK_P/DIFF_SYSCLK_N inputs to the processor, which is in turn used to supply clocks to the core and platform (SYSCLK), DDR controller (DDRCLK) and USB controller (USBCLK). 2.6.2 SerDes clocks The LS1021A SerDes port accepts two different differential clock inputs (SD1_REFCLK1 and SD1_REFCLK2), allowing the flexibility to use different protocols with different clock rates on the SerDes pins. The clock inputs are provided by the IDT clock generator device, which can generate the required 100.00 or 125.00 frequencies. 2.6.3 Ethernet and USB clocks Ethernet clock is also provided by an IDT6V49205BNLGI, which supplies 125.0 MHz to the Ethernet port clock inputs (EC3_GTXCLK_125), as well as to the separate RGMII PHYs. Additionally, a 60 MHz reference clock is provided for the USBCLK input from external USB PHY. Additionally, for the Ethernet PHY input clocks are individually supplied by IDT6V49205BNLGI as well. 2.7 Memory controllers The TWR-LS1021A supports high-speed DRAM with 1 GB DDR3L SDRAM discrete devices (32-bit bus). The memory interface includes all the necessary termination and I/O power, and is routed so as to achieve maximum performance of the memory bus, as shown in Figure 2-7. |
유사한 부품 번호 - TWR-LS1021A |
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유사한 설명 - TWR-LS1021A |
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