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BS616UV4016 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Brilliance Semiconductor

๋ถ€ํ’ˆ๋ช… BS616UV4016
์ƒ์„ธ๋‚ด์šฉ  Ultra Low Power/High Speed CMOS SRAM 256K X 16 Bit
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BS616UV4016 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Brilliance Semiconductor

 
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BSI
BS616UV4016
4
R0201-BS616UV4016
Revision
1.3
Sep.
2005
n DATA RETENTION CHARACTERISTICS (T
A = -40
OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
VDR
VCC for Data Retention
CEโ‰งVCC-0.2V,
VINโ‰งVCC-0.2V or VINโ‰ฆ0.2V
1.2
--
--
V
ICCDR
(3)
Data Retention Current
CEโ‰งVCC-0.2V,
VINโ‰งVCC-0.2V or VINโ‰ฆ0.2V
--
0.15
1.7
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
tR
Operation Recovery Time
See Retention Waveform
tRC
(2)
--
--
ns
1. VCC=1.2V, TA=25
OC.
2. tRC = Read Cycle Time.
3. ICCRD_Max. is 1.2uA at TA=70
OC.
n LOW V
CC DATA RETENTION WAVEFORM (1) (CE Controlled)
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
Output Load
Others
CL = 30pF+1TTL
1. Including jig and scope capacitance.
n KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM
โ€œHโ€ TO โ€œLโ€
WILL BE CHANGE
FROM
โ€œHโ€ TO โ€œLโ€
MAY CHANGE
FROM
โ€œLโ€ TO โ€œHโ€
WILL BE CHANGE
FROM
โ€œLโ€ TO โ€œHโ€
DON
โ€™T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
โ€œOFFโ€ STATE
CL
(1)
1 TTL
Output
ALL INPUT PULSES
โ†’ โ†
90%
VCC
GND
Rise Time:
1V/ns
Fall Time:
1V/ns
90%
โ†’ โ†
10%
10%
Data Retention Mode
VCC
tCDR
VCC
tR
VIH
VIH
CEโ‰งVCC - 0.2V
VDRโ‰ง1.0V
CE
VCC


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