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A81L801 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - AMIC Technology

๋ถ€ํ’ˆ๋ช… A81L801
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM
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์ œ์กฐ์‚ฌ  AMICC [AMIC Technology]
ํ™ˆํŽ˜์ด์ง€  http://www.amictechnology.com
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A81L801 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - AMIC Technology

 
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A81L801
Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit
Boot Sector Flash Memory and 128K x 8 Bit Low Voltage CMOS SRAM
Preliminary
PRELIMINARY
(March, 2005, Version 0.0)
1
AMIC Technology, Corp.
MCP Features
Single power supply operation 2.7 to 3.6 volt
High Performance
- Access time as fast as 70ns
Package
- 69-Ball FBGA (8x11x1.4 mm)
Industrial operating temperature range: -25
ยฐC to 85ยฐC for โ€“I
Flash Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
Access times:
- 70 (max.)
Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector.
Temporary Sector Unprotect feature allows code changes
in previously locked sectors
Extended operating temperature range: -25
ยฐC ~ +85ยฐC for โ€“
I series
Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple
program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125
ยฐC
- Reliable operation for the life of the system
Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Ready /
BUSY pin (RY / BY )
- Provides a hardware method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin ( RESET )
- Hardware method to reset the device to reading array data
LP SRAM Features
Power supply range: 2.7V to 3.6V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 30mA(max.)
Standby: 5uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
Data retention voltage: 2.0V (min.)


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