PRELIMINARY

KM732V696/L

64Kx32 Synchronous SRAM

Rev 1.0

- 2 -

May 1997

WEc

WEd

64Kx32-Bit Synchronous Pipelined Burst SRAM

The KM732V696/L is a 2,097,152 bit Synchronous Static Ran-

dom Access Memory designed for high performance second

level cache of Pentium and Power PC based System.

It is organized as 64K words of 32bits and integrates address

and control registers, a 2-bit burst address counter and added

some new functions for high performance cache RAM applica-

tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed

and synchronous.

Full bus-width write is done by GW, and each byte write is per-

formed by the combination of WEx and BW when GW is high.

Burst cycle can be initiated with either the address status pro-

cessor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated internally in

the system

′s burst sequence and are controlled by the burst

address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(linear

or interleaved).

ZZ pin controls Power Down State and reduces Stand-by cur-

rent regardless of CLK.

The KM732V696/L is fabricated using SAMSUNG

′s high per-

formance CMOS technology and is available in a 100pin TQFP

package. Multiple power and ground pins are utilized to mini-

mize ground bounce.

GENERAL DESCRIPTION

FEATURES

LOGIC BLOCK DIAGRAM

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

±5% Power Supply for 2.5V I/O

• I/O Supply Voltage : 3.3V-5%/+10% for 3.3V I/O

or 2.5V+0.4V/-0.13V for 2.5V I/O

• 5V Tolerant Inputs except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a

linear burst.

• Three Chip Enables for simple depth expansion with No Data

Contention ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

• 100-TQFP-1420A

CLK

LBO

ADV

ADSC

ADSP

GW

BW

WEa

WEb

OE

ZZ

BURST CONTROL

LOGIC

BURST

64Kx32

ADDRESS

CONTROL

OUTPUT

DATA-IN

ADDRESS

COUNTER

MEMORY

ARRAY

REGISTER

REGISTER

BUFFER

LOGIC

A

REGISTER

FAST ACCESS TIMES

Parameter

Symbol

-13

-15

Unit

Cycle Time

13

15

ns

Clock Access Time

7

8

ns

Output Enable Access Time

6

7

ns