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MC14015BD 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC14015BD 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14015B/D MC14015B Dual 4-Bit Static Shift Register The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master–slave flip–flops. Data is shifted from one stage to the next during the positive–going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired. • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Flip–Flop Design — Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse. • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range. MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 3.) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Device Package Shipping ORDERING INFORMATION MC14015BCP PDIP–16 2000/Box MC14015BD SOIC–16 48/Rail MC14015BDR2 SOIC–16 2500/Tape & Reel 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14015BCP AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 16 14015B AWLYWW SOEIAJ–16 F SUFFIX CASE 966 1 16 MC14015B AWLYWW TSSOP–16 DT SUFFIX CASE 948F 14 015B ALYW 1 16 MC14015BDT TSSOP–16 2000/Tape & Reel MC14015BF SOEIAJ–16 See Note 1. MC14015BFEL SOEIAJ–16 See Note 1. |
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