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MC14013 데이터시트(PDF) 1 Page - ON Semiconductor

부품명 MC14013
상세설명  Dual Type D Flip-Flop
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14013B/D
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip–flops for counter and toggle applications.
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4013B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14013BCP
PDIP–14
2000/Box
MC14013BD
SOIC–14
55/Rail
MC14013BDR2
SOIC–14
2500/Tape & Reel
MC14013BDT
TSSOP–14
MC14013BF
SOEIAJ–14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC14013BCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
14013B
AWLYWW
14
013B
ALYW
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14013B
AWLYWW
MC14013BFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14013BDTR2
TSSOP–14 2500/Tape & Reel


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