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74AUP1G32GM 데이터시트(PDF) 10 Page - NXP Semiconductors |
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74AUP1G32GM 데이터시트(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 10 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 13. Waveforms CL = 15 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V 3.0 15.6 3.0 17.2 ns VCC = 1.4 V to 1.6 V 2.0 9.8 2.0 10.8 ns VCC = 1.65 V to 1.95 V 1.8 7.9 1.8 8.7 ns VCC = 2.3 V to 2.7 V 1.6 6.3 1.6 6.9 ns VCC = 3.0 V to 3.6 V 1.5 5.8 1.5 6.4 ns CL = 30 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V 4.0 21.5 4.0 23.7 ns VCC = 1.4 V to 1.6 V 2.9 13.3 2.9 14.7 ns VCC = 1.65 V to 1.95 V 2.4 10.7 2.4 11.8 ns VCC = 2.3 V to 2.7 V 2.2 8.4 2.2 9.3 ns VCC = 3.0 V to 3.6 V 2.1 7.7 2.1 8.5 ns Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max Measurement points are given in Table 11. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 6. The data input (A or B) to output (Y) propagation delays Table 11: Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns mna615 tPHL tPLH VM VM A, B input Y output GND VI VOH VOL |
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