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CS4384-DQZ 데이터시트(PDF) 3 Page - Cirrus Logic |
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CS4384-DQZ 데이터시트(HTML) 3 Page - Cirrus Logic |
3 / 50 page DS620A1 3 CS4384 5.2.4 DAC Pair Disable (DACx_DIS) ............................................................................................ 35 5.2.5 Power Down (PDN).............................................................................................................. 35 5.3 PCM Control (address 03h) ........................................................................................................... 35 5.3.1 Digital Interface Format (DIF)............................................................................................... 35 5.3.2 Functional Mode (FM) .......................................................................................................... 36 5.4 DSD Control (address 04h) ........................................................................................................... 36 5.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 36 5.4.2 Direct DSD Conversion (DIR_DSD) ..................................................................................... 37 5.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 37 5.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 37 5.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 37 5.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 38 5.5 Filter Control (address 05h) ........................................................................................................... 38 5.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 38 5.6 Invert Control (address 06h) .......................................................................................................... 38 5.6.1 Invert Signal Polarity (INV_xx) ............................................................................................. 38 5.7 Group Control (address 07h) ......................................................................................................... 38 5.7.1 Mutec Pin Control (MUTEC) ................................................................................................ 38 5.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 39 5.7.3 Single Volume Control (SNGLVOL) ..................................................................................... 39 5.8 Ramp and Mute (address 08h) ...................................................................................................... 39 5.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 39 5.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 40 5.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ................................................... 40 5.8.4 PCM Auto-Mute (PAMUTE) ................................................................................................. 40 5.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 40 5.8.6 MUTE Polarity and DETECT (MUTEP1:0)........................................................................... 41 5.9 Mute Control (address 09h) ........................................................................................................... 41 5.9.1 Mute (MUTE_xx) .................................................................................................................. 41 5.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h).............................................................................. 41 5.10.1 De-Emphasis Control (PX_DEM1:0) .................................................................................. 41 5.11 ATAPI Channel Mixing and Muting (ATAPI) ................................................................................ 42 5.12 Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ........................................... 43 5.12.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 43 5.13 PCM Clock Mode (address 16h).................................................................................................. 43 5.13.1 Master Clock Divide by 2 Enable (MCLKDIV) .................................................................... 43 6. FILTER RESPONSE PLOTS ............................................................................................................... 44 7. REFERENCES...................................................................................................................................... 48 8. PARAMETER DEFINITIONS................................................................................................................ 48 9. PACKAGE DIMENSIONS .................................................................................................................... 49 10. ORDERING INFORMATION .............................................................................................................. 50 11. REVISION HISTORY ......................................................................................................................... 50 |
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