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CS4922-CL 데이터시트(PDF) 8 Page - Cirrus Logic |
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CS4922-CL 데이터시트(HTML) 8 Page - Cirrus Logic |
8 / 34 page CS4922 8 SWITCHING CHARACTERISTICS - CONTROL PORT (SPI MODE) (T A = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) Notes: 6. Data must be held for sufficient time to bridge 300(50) ns transition time of SCK/SCL. 7. CDOUT should NOT be sampled during this time period. 8. REQ will only go HIGH if there is no data in SCPOUT at the rising edge of SCL/SCK during a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 k Ω. C L = 20 pF. 9. If REQ went HIGH as indicated in note 7, then REQ will hold high at least until the next rising edge of SCK/SCL. If data is in SCPOUT at this time REQ will go active LOW again. This condition should be treated as a new READ process. Address and R/W bit should be sent again. Parameter Symbol Min Max Units SPI Mode (CS = 0) SCK/SCL Clock Frequency (slow mode) (fast mode) fsck fsck - - 350 2000 kHz CS Falling to SCK/SCL Rising (slow mode) tcss 20 - ns Rise Time of Both CDIN and SCK/SCL Lines (slow mode) tr -50 ns Fall Time of Both CDIN and SCK/SCL Lines (slow mode) (fast mode) tf tf - - 300 50 ns ns SCK/SCL Low Time (slow mode) (fast mode) tscl tscl 1100 150 - - ns ns SCK/SCL High Time (slow mode) (fast mode) tsch tsch 1100 150 - - ns ns Setup Time CDIN to SCK/SCL Rising (slow mode) (fast mode) tcdisu 250 50 - - ns ns Hold Time SCK/SCL Rising to CDIN (Note 6) tcdih 50 - ns Transition Time from SCK/SCL to CDOUT Valid (Note 7) tscdov -40 ns Time from SCK/SCL Rising to REQ Rising (Note 7) tscrh -200 ns Rise Time for REQ (Note 8) trr -50 ns Fall Time for REQ (Note 9) trf -20 ns Hold Time for REQ from SCK/SCL Rising (Note 9) tscrl 0- ns Time from SCK/SCL Falling to CS Rising tsccsh 20 - ns High Time Between Active CS tcsht 200 - ns |
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