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X1243V8 데이터시트(PDF) 6 Page - Intersil Corporation |
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X1243V8 데이터시트(HTML) 6 Page - Intersil Corporation |
6 / 17 page 6 FN8249.0 April 28, 2005 In an alternative mode (called pulsed interrupt mode), controlled by an interrupt mode (IM) bit, the alarm 0 setting provides an output pulse on IRQ each time the alarm matches the RTC. In this case the AL0 bit is not used. Alarm 1 works as before (i.e. the AL1 bit is set when an alarm occurs), but it is necessary to poll the sta-tus register to determine whether a match has occurred. This read operation is necessary to reset the AL1 ag. Normal Mode (IM Bit = 0) A match of the RTC and the contents of the alarm 0 registers automatically sets the AL0 bit. If the AL0E bit is also set, the output IRQ signal goes active (LOW). If the AL0E bit is not set, the AL0 bit is set, but the IRQ signal remains unchanged. A match of the RTC and the contents of the alarm 1 registers automatically sets the AL1 bit. If the AL1E bit is also set, the output IRQ signal goes active (LOW). If the AL1E bit is not set, the AL1 bit is set, but the IRQ signal remains unchanged. Reading the status register, containing the AL0 and AL1 bits, resets the bits. The bits do not reset until the falling edge of the 8th output clock of the status register containing the Alarm bits. When the bits reset, the output IRQ signal returns to the inactive state. Pulsed Interrupt Mode (IM Bit = 1) In this mode, the alarm interrupt enable bits (AL0E and AL1E) are not used. Alarm 1 operates as before, so a match of the RTC and Alarm 1 sets the AL1 bit. Since the interrupt enable bits have no function, it is neces-sary for the host processor to poll the AL1 bit to deter-mine if an alarm has occurred. Alarm 0 provides an output response. In this case, when the RTC matches the Alarm 0 registers, the output IRQ pulses one time. This pulse can be used to control some outside circuit or event, without the need for a local processor. The duration of the pulse is 1024 cycles of the 32.748kHz oscillator. All alarm 0 enable options are available, so this becomes a very exible long term repeat trigger. Writing To The Clock/Control Registers Changing any of the nonvolatile bits of the clock/control register requires the following steps: - Write a 02H to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation pre-ceeded by a start and ended with a stop). - Write a 06H to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). - Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the CCR changes EEPROM values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. Writes to undened areas have no effect. The RWEL bit is reset by the completion of a nonvolatile write write cycle, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by send-ing an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. - Writing all zeros to the status register resets both the WEL and RWEL bits. - A read operation occurring between any of the previ-ous operations will not interrupt the register write operation. - The RWEL and WEL bits can be reset by writing a 0 to the Status Register. Serial Communication Interface Conventions The device supports a bidirectional bus oriented proto-col. The protocol denes any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. SCL SDA Data Stable Data Change Data Stable FIGURE 3. VALID DATA CHANGES ON THE SDA BUS X1243 |
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유사한 설명 - X1243V8 |
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