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AD7791BRM 데이터시트(PDF) 1 Page - Analog Devices |
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AD7791BRM 데이터시트(HTML) 1 Page - Analog Devices |
1 / 20 page Low Power, Buffered 24-Bit Sigma-Delta ADC AD7791 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. FEATURES Power Supply: 2.5 V to 5.25 V operation Normal: 75 µA max Power-down: 1 µA max RMS noise: 1.1 µV at 9.5 Hz update rate 19.5-bit p-p resolution (22 bits effective resolution) Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillator Rail-to-rail input buffer VDD monitor channel Temperature range: –40°C to +105°C 10-lead MSOP INTERFACE 3-wire serial SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK APPLICATIONS Smart transmitters Battery applications Portable instrumentation Sensor measurement Temperature measurement Pressure measurement Weigh scales 4 to 20 mA loops FUNCTIONAL BLOCK DIAGRAM DOUT/RDY DIN SCLK CS 04227-0-001 SERIAL INTERFACE CLOCK Σ-∆ ADC AIN(–) AIN(+) GND REFIN(+) REFIN(–) AD7791 VDD BUF VDD GND Figure 1. GENERAL DESCRIPTION The AD7791 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 24-bit ∑-∆ ADC with one differential input that can be buffered or unbuffered. The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduc- tion in the current consumption. The update rate, cutoff frequency, and settling time will scale with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP. |
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