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AM45DL3208G 데이터시트(HTML) 5 Page - Advanced Micro Devices

부품명 AM45DL3208G
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Download  66 Pages
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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AM45DL3208G 데이터시트(HTML) 5 Page - Advanced Micro Devices

 
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March 12, 2004
Am45DL3208G
3
PR EL I M I N ARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH;
PSRAM Byte Mode, CIOs = VSS ....................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VSS;
PSRAM Word Mode, CIOs = VCC ..................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL;
PSRAM Byte Mode, CIOs = V
SS ....................................................13
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Table 5. Top Boot Sector Addresses .............................................15
Table 7. Bottom Boot Sector Addresses .........................................17
Sector/Sector Block Protection and Unprotection .................. 19
Table 9. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Table 10. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Write Protect (WP#) ................................................................ 20
Temporary Sector Unprotect .................................................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Figure 3. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ...................................................... 23
Low V
CC Write Inhibit ........................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Flash Command Definitions . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 27
Byte/Word Program Command Sequence ............................. 28
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation .......................................................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 5. Erase Operation............................................................... 30
Flash Write Operation Status . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
Figure 6. Data# Polling Algorithm .................................................. 33
RY/BY#: Ready/Busy# ............................................................ 34
DQ6: Toggle Bit I .................................................................... 34
Figure 7. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
Table 17. Write Operation Status ................................................... 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37
Figure 8. Maximum Negative Overshoot Waveform ...................... 37
Figure 9. Maximum Positive Overshoot Waveform........................ 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38
CMOS Compatible .................................................................. 38
Figure 10. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 39
Figure 11. Typical I
CC1 vs. Frequency ............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Test Setup.................................................................... 41
Figure 13. Input Waveforms and Measurement Levels ................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Pseudo SRAM CE#s Timing ................................................... 42
Figure 14. Timing Diagram for Alternating
Between Pseudo SRAM and Flash................................................ 42
Read-Only Operations ........................................................... 43
Figure 15. Read Operation Timings ............................................... 43
Hardware Reset (RESET#) .................................................... 44
Figure 16. Reset Timings ............................................................... 44
Word/Byte Configuration (CIOf) .............................................. 45
Figure 17. CIOf Timings for Read Operations................................ 45
Figure 18. CIOf Timings for Write Operations................................ 45
Flash Erase and Program Operations .................................... 46
Figure 19. Program Operation Timings.......................................... 47
Figure 20. Accelerated Program Timing Diagram.......................... 47
Figure 21. Chip/Sector Erase Operation Timings .......................... 48
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 49
Figure 23. Data# Polling Timings (During Embedded Algorithms). 49
Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 25. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect .................................................. 51
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 51
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 52
Alternate CE#f Controlled Erase and Program Operations .... 53
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
Power Up Time ....................................................................... 55
Read Cycle ............................................................................. 55
Figure 29. Pseudo SRAM Read Cycle—Address Controlled......... 55
Read Cycle ............................................................................. 56
Figure 30. Pseudo SRAM Read Cycle........................................... 56
Write Cycle ............................................................................. 57
Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 57
Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 58
Figure 33. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 59
Flash Erase And Programming Performance . . 60
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 60


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