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AM45DL3208GB70IT 데이터시트(PDF) 11 Page - Advanced Micro Devices |
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AM45DL3208GB70IT 데이터시트(HTML) 11 Page - Advanced Micro Devices |
11 / 66 page March 12, 2004 Am45DL3208G 9 PR EL I M I N ARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am45DL320 8 G T 70 I T TAPE AND REEL T= 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT SECTOR T = Top boot B = Bottom boot PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY 8= 8 Mbits AMD DEVICE NUMBER/DESCRIPTION Am45DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM Valid Combinations Order Number Package Marking Am45DL3208GT70I Am45DL3208GB70I T, S M450000008 M450000009 Am45DL3208GT85I Am45DL3208GB85I T, S M45000000A M45000000B |
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