전자부품 데이터시트 검색엔진 |
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ISL23711 데이터시트(PDF) 5 Page - Intersil Corporation |
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ISL23711 데이터시트(HTML) 5 Page - Intersil Corporation |
5 / 9 page 5 FN6127.0 August 16, 2005 SDA vs SCL Timing A0, A1 Pin Timing tDH Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 0ns tR (Note 14) SDA, SCL, A0, A1 Rise Time From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns tF (Note 14) SDA, SCL, A0, A1 Fall Time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb (Note 14) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu (Note 14) SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2~2.5k Ω For Cb = 40pF, max is about 15~20k Ω 1k Ω tSU:A A0, A1 Setup Time Before START condition 600 ns tHD:A A0, A1 Hold Time After STOP condition 600 ns Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNIT tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (INPUT TIMING) SDA (OUTPUT TIMING) tF tLOW tBUF tAA tR tHD:A SCL SDA IN A0, A1 tSU:A Clk 1 START STOP ISL23711 |
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