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AM42BDS640AG 데이터시트(PDF) 41 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42BDS640AG 데이터시트(HTML) 41 Page - SPANSION

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Am42BDS640AG
November 1, 2002
P R E L I M INARY
FLASH AC CHARACTERISTICS
Synchronous/Burst Read
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
D8
(54 MHz)
C8
(40 MHz)
Unit
JEDEC
Standard
tIACC
Latency (Even Address in Reduced Wait-State
Handshaking Mode)
Max
87.5
95
ns
Parameter
Description
D8, D9
(54 MHz)
C8, C9
(40 MHz)
Unit
JEDEC
Standard
t
IACC
Latency—(Odd Address in Handshaking mode or
Standard Handshaking)
Max
106
120
ns
t
BACC
Burst Access Time Valid Clock to Output Delay
Max
13.5
20
ns
t
ACS
Address Setup Time to CLK (Note 1)
Min
5
ns
t
ACH
Address Hold Time from CLK (Note 1)
Min
7
ns
t
BDH
Data Hold Time from Next Clock Cycle
Max
4
ns
t
OE
Output Enable to Output Valid
Max
13.5
20
ns
t
CEZ
Chip Enable to High Z
Max
10
ns
t
OEZ
Output Enable to High Z
Max
10
ns
t
CES
CE# Setup Time to CLK
Min
5
ns
t
RDYS
RDY Setup Time to CLK
Min
5
ns
t
RACC
Ready Access Time from CLK
Max
13.5
20
ns
t
AAS
Address Setup Time to AVD# (Note 1)
Min
5
ns
t
AAH
Address Hold Time to AVD# (Note 1)
Min
7
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
t
AVC
AVD# Low to CLK
Min
5
ns
t
AVD
AVD# Pulse
Min
12
ns
t
ACC
Access Time
Max
70
ns


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