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AM42BDS640AG 데이터시트(PDF) 46 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42BDS640AG 데이터시트(HTML) 46 Page - SPANSION

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November 1, 2002
Am42BDS640AG
45
P R E L I M INARY
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under
a CLK synchronous burst mode.
Figure 16.
Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address
Da
Da + 1
Da + n
OE#
DQ15-DQ0
A21-A0
Aa
AVD#
RDY
CLK
CE#f
tCAS
tAAS
tAVC
tAVD
tAAH
tOE
tRACC
tOEZ
tCEZ
tIACC
tBDH
7 cycles for initial access shown.
Hi-Z
Hi-Z
Hi-Z
12
3
4
56
7
tRDYS
tBACC
tACC


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