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AM42BDS640AG 데이터시트(PDF) 48 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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November 1, 2002
Am42BDS640AG
47
P R E L I M INARY
AC CHARACTERISTICS
Asynchronous Read
Notes:
1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.
2. Not 100% tested.
Note: RA = Read Address, RD = Read Data.
Figure 18.
Asynchronous Mode Read with Latched Addresses
Parameter
Description
D8, D9
(54 MHz)
C8, C9
(40 MHz)
Unit
JEDEC
Standard
t
CE
Access Time from CE# Low
Max
70
85
ns
t
ACC
Asynchronous Access Time (Note 1)
Max
70
85
ns
t
AVDP
AVD# Low Time
Min
12
ns
t
AAVDS
Address Setup Time to Rising Edge of AVD
Min
5
ns
t
AAVDH
Address Hold Time from Rising Edge of AVD
Min
7
ns
t
OE
Output Enable to Output Valid
Max
13.5
20
ns
t
OEH
Output Enable Hold
Time
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OEZ
Output Enable to High Z (Note 2)
Max
10
10.5
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
tCE
WE#
A21-A0
CE#f
OE#
Valid RD
tACC
tOEH
tOE
DQ15-DQ0
tOEZ
tAAVDH
tAVDP
tAAVDS
AVD#
RA
tCAS


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