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AM42BDS640AG 데이터시트(PDF) 53 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42BDS640AG 데이터시트(HTML) 53 Page - SPANSION

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Am42BDS640AG
November 1, 2002
P R E L I M INARY
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. CLK can be either V
IL or VIH.
5. The Asynchronous programming operation is
independent of the Set Device Read Mode bit in the Burst
Mode Configuration Register.
6. AVD# must toggle during command sequence if CLK is at
V
IH.
Figure 22.
Alternate Asynchronous Program Operation Timings
OE#
CE#f
Data
Addresses
AVD#
WE#
CLK
VCC
555h
PD
tAS
tAVSW
tAVHW
tCHW
tAH
tWC
tWPH
PA
tVCS
tWP
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
tDS
VIH
VIL
tAVDP
A0h
tCS
(Note 4)


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