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AM42BDS640AG 데이터시트(PDF) 15 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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Am42BDS640AG
November 1, 2002
P R E L I M INARY
39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence
begins with the starting address written to the device,
but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word
Linear Wrap modes begin their burst sequence on the
starting address written to the device, and then wrap
back to the first address in the selected address group.
Note that in these three burst read modes the
address pointer does not cross the boundary that
occurs every 64 words; thus, no wait states are
inserted (except during the initial access).
The RDY pin indicates when data is valid on the bus.
The devices can wrap through a maximum of 128
words of data (8 words up to 16 times, 16 words up to
8 times, or 32 words up to 4 times) before requiring a
new synchronous access (latching of a new address).
Burst Mode Configuration Register
The device uses a configuration register to set the
various burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Reduced Wait-State Handshaking Option
The device can be equipped with a reduced wait-state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to deter-
mine when the initial word of burst data is ready to be
read. The host system should use the programmable
wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after
OE# goes low.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect
command sequence to the device. See “Autoselect
Command Sequence” for details.
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock frequency
and the presence of a boundary crossing. See “Set
Burst Mo de Configurat ion Re gister Command
Sequence” section on page 23 section for more infor-
mation. The device will automatically delay RDY and
data by one additional clock cycle when the starting
address is odd.
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in another
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being erased).
Figure 33, “Back-to-Back Read/Write Cycle Timings,”
on page 62 shows how read and write cycles may be
initiated for simultaneous operation with zero latency.
R e fe r t o th e DC Ch ar ac te r i s t ic s tab l e f o r
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. During a
synchronous write operation, to write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to
VIH when providing an address to the device, and drive
WE# and CE# to VIL, and OE# to VIH. when writing
commands or data. During an asynchronous write
operation, the system must drive CE# and WE# to VIL
and OE# to VIH when providing an address, command,
and data. The asynchronous and synchronous pro-
graming operation is independent of the Set Device
Read Mode bit in the Burst Mode Configuration Reg-
ister.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 8, “Programmable Wait
State Settings,” on page 24 indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks B and C contain
only 32 Kword sectors, while Banks A and D contain
both 8 Kword boot sectors in addition to 32 Kword sec-
tors. A “bank address” is the address bits required to
uniquely select a bank. Similarly, a “sector address” is
the address bits required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. ACC is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts V
ID on this input, the device auto-
matically enters the aforementioned Unlock Bypass


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