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AM42BDS640AG 데이터시트(PDF) 16 Page - SPANSION

부품명 AM42BDS640AG
부품 상세설명  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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November 1, 2002
Am42BDS640AG
15
P R E L I M INARY
mode and uses the higher voltage on the input to
reduce the time required for program operations. The
system would use a two-cycle program command
sequence as required by the Unlock Bypass mode.
Removing V
ID from the ACC input returns the device to
normal operation. Note that sectors must be unlocked
prior to raising ACC to V
ID. Note that the ACC pin must
not be at V
ID for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
When at V
IL, ACC locks all sectors. ACC should be at
V
IH for all other conditions.
Autoselect Functions
If the sy stem writes the autoselect c o mmand
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ15–DQ0. Autoselect mode may only be
entered and used when in the asynchronous read
mode. Refer to the “Autoselect Command Sequence”
section on page 26 section for more information.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at V
CC ± 0.2 V.
The device requires standard access time (t
CE) for read
access, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the opera-
tion is completed.
I
CC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. While in asynchronous mode, the
de vice au to matically enables this mo de w hen
addresses remain stable for tACC + 60 ns. The auto-
matic sleep mode is independent of the CE#, WE#, and
OE# control signals. Standard address access timings
provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either
the first active CLK edge occurs after tACC or the CLK
runs slower than 5MHz. Note that a new burst opera-
tion is required to provide new data.
I
CC4 in the “Flash DC Characteristics” section on page
36 represents the automatic sleep mode current spec-
ification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of
resetting the device to reading array data. When
RESET# is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS ± 0.2 V, the device
draws CMOS standby current (I
CC4). If RESET# is held
at V
IL but not within VSS ± 0.2 V, the standby current will
be greater.
RESET# may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the device requires a time of t
READY (during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a
program or erase operation is not executing, the reset
operation is completed within a time of t
READY (not
during Embedded Algorithms). The system can read
data t
RH after RESET# returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 20, “Reset Timings,” on
page 49 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The outputs are placed in the high imped-
ance state.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 14, “Com-
mand Definitions,” on page 30 for command defini-
tions).
The device offers two types of data protection at the
sector level:
■ The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.


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