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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM42BDS640AG 데이터시트(PDF) 25 Page - SPANSION |
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AM42BDS640AG 데이터시트(HTML) 25 Page - SPANSION |
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25 / 72 page  24 Am42BDS640AG November 1, 2002 P R E L I M INARY Table 8. Programmable Wait State Settings Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. 3. Assumes even address. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default set- ting. Handshaking Option If the device is equipped with reduced wait-state hand- shaking, the host system should set address bits A14–A12 to 010 for a clock frequency of 40 MHz or to 011 f o r a c l ock f r e quency of 54 MHz f o r the system/device to execute at maximum speed. Table 9 describes the typical number of clock cycles (wait states) for various conditions. Table 9. Initial Access Codes * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. Standard Handshaking Operation For optimal burst mode performance on devices with standard handshaking, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Table 10 describes the typical number of clock cycles (wait states) for various conditions with A14–A12 set to 101. Table 10. Wait States for Standard Handshaking * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). Burst Read Mode Configuration The device supports four different burst read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then proceeds until the next 8 word boundary. The address pointer then returns to the first word of the boundary, wrapping back to the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 11 shows the address bits and settings for the four burst read modes. A14 A13 A12 Total Initial Access Cycles 00 0 2 00 1 3 01 0 4 01 1 5 10 0 6 10 1 7 System Frequency Range Device Speed Rating 6–11 MHz 2 2 3 4 40 MHz 12–23 MHz 2 3 4 5 24–33 MHz 3 4 5 6 34–40 MHz 4 5 6 7 40–47 MHz 4 5 6 7 54 MHz 48–54 MHz 5 6 7 8 Conditions at Address Typical No. of Clock Cycles after AVD# Low 40/54 MHz Initial address is even 7 Initial address is odd 7 Initial address is even, and is at boundary crossing* 7 Initial address is odd, and is at boundary crossing* 7 |
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