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DAC650

7

TECHNOLOGY OVERVIEW

The DAC650 uses a unique design approach to achieve very

fast settling time and high resolution. This mixed-technol-

ogy design uses two active chips: one gallium arsenide and

the other silicon.

The GaAs MESFET die is used for those circuits which

determine speed. This includes the latches, data decoders,

and current switches. A silicon die with thin film is used for

those circuits which determine accuracy, such as the preci-

sion references and current sources. The precision R-2R

resistor ladders are laser trimmed to further increase the

accuracy of the DAC650. A block diagram of the DAC650

is shown in Figure 1.

THEORY OF OPERATION

The DAC650 employs a familiar architecture where input

bits switch on the appropriate current sources. Bits 1-3 are

decoded into 7 segments before the first set of latches. A

similar delay is given for the 9 least significant bits to

minimize data skew. The edge triggered master-slave latches

are driven by an internal clock buffer. This buffer placement

has matched the clock lines to each of the 32 latches, thus

minimizing output glitch energy.

There are 7 current sources for bits 1 to 3. Current sources

for bits 4-8 are scaled down in binary fashion. These current

sources are switched directly to the output of the R-2R

ladder. Bits 9-12 are fed to the laser trimmed R-2R ladder for

proper scale-down. The segmentation further minimizes

output glitch which can cause spectral degradation.

The output current sees 50

Ω of output impedance from the

equivalent resistance of a R-2R ladder (100

Ω) in parallel

with 100

Ω (Figure 1). With all of the current sources off, the

output voltage is at +1V. With all current sources on

(–40mA), the output voltage is at –1V. There is also a

with 50

Ω. This gives an output swing of 1Vp-p with an

external 50

Ω load.

REFERENCE/GAIN ADJUSTMENT

A precision +10V reference is included in the DAC650. A

50

Ω resistor should be connected between REF

for the specified unadjusted gain. This internal reference has

been laser trimmed to minimize offset and gain drift. Alter-

natively, an external reference may be used. Multiple DACs

may be run from one master reference by connecting a 50

Ω

potentiometer may be used in place of the 50

Ω resistor in

order to provide a

±1% gain adjustment range (Figure 2).

A wider adjustment range of

±20% may be achieved by

connecting a 10k

Ω potentiometer from REF

output to more than 40mA full scale may degrade high

frequency performance and reliability due to higher current

densities and operating temperature. Alternatively, lower

full scale currents will affect operation because there is less

current available to charge internal and external capaci-

tances.

It should be noted that the gain adjust techniques mentioned

above affect the current output and thus the voltage output

from the DAC650. The voltage output will also be affected

by an external load acting in parallel with the 50

Ω output

impedance.

OFFSET ADJUST

The offset may be adjusted by connecting a potentiometer

between the +5V supply and ground with the wiper con-

nected to the offset adjust pin. The voltage on this pin with

no connection is about 2V, with an equivalent impedance of

1.6k

Ω. A 10kΩ potentiometer will give the necessary ad-

justment range. The full scale range of the DAC output may

be offset so it is not symmetrical around zero, but the full

scale range must also be adjusted so that the output swing

does not exceed

±1V. Connecting the offset adjust pin to

ground gives a unipolar output of 0 to –2V (with no load) or

0 to –1V (with a 50

Ω load). This also reduces the current

requirements for the +5V supply by 20mA.

DIGITAL INPUTS, LOGIC THRESHOLDS,

and TERMINATION

The input logic levels and clock levels are ECL compatible.

The data inputs are single ended ECL and the clock input is

differential.

The internal impedance of the data and clock inputs is a high

impedance (FET gate), and is clamped to the digital supply

and ground to protect against ESD damage. ESD precau-

tions should still be used when handling the DAC650.

The inputs will most likely be driven by high-speed ECL

gate outputs. These outputs should be terminated using

standard high-speed transmission line techniques. Consult

an ECL handbook for proper methods of termination.

Termination resistors should not be connected to the analog

ground plane close to the DAC650. The fast changing digital

bit currents will cause noise in the analog ground plane

under this layout scheme. These fast changing digital cur-

rents should be steered away from the sensitive DAC650

analog ground plane. For speeds of up to 256MHz, series

termination with 47

Ω resistors will be adequate

(Figure 3). This termination technique will greatly lessen the

issue of termination currents coupling into the analog ground

plane. Above 256MHz, parallel termination of the transmis-

sion line at the package pin may be required for clean digital

input.

The input data threshold level is set by connecting the

appropriate voltage (–1.2V to –1.4V) to pin 1. The actual

level may be provided 3 ways:

(1) The user connects the DAC650’s internal –1.3V thresh-

old reference directly to pin 1. This simple connection

provides excellent noise margins for ECL levels.