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LP5910-1.8YKAR 데이터시트(PDF) 15 Page - Texas Instruments |
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LP5910-1.8YKAR 데이터시트(HTML) 15 Page - Texas Instruments |
15 / 35 page 15 LP5910 www.ti.com SNVSA91E – SEPTEMBER 2015 – REVISED JULY 2017 Product Folder Links: LP5910 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. Also, the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed. 8.2.2.6 Remote Capacitor Operation The LP5910 requires at least a 1-µF capacitor at the OUT pin, but there is no strict requirements about the location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10 cm away from the LDO. This means that there is no need to have a special capacitor close to the OUT pin if there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote capacitor feature helps user to minimize the number of capacitors in the system. As a good design practice, keep the wiring parasitic inductance at a minimum, using as wide as possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many vias as possible between the connection layers. It is recommended to keep parasitic wiring inductance less than 35 nH. For the applications with fast load transients, an input capacitor is recommended, equal to or larger to the sum of the capacitance at the output node, for the best load-transient performance. 8.2.2.7 No-Load Stability The LP5910 remains stable, and in regulation, with no external load. 8.2.2.8 Enable Control The LP5910 may be switched to an ON or OFF state by a logic input at the EN pin. A voltage on this pin greater than VIH turns the device on, while a voltage less than VIL turns the device off. When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA. Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged to ground. If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to keep the regulator output permanently on. An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics under VIL and VIH. Table 2. Recommended Output Capacitor Specification PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Output capacitor, COUT Capacitance for stability 0.7 1 10 µF ESR 5 500 mΩ 8.2.2.9 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1. PD(MAX) = (VIN(MAX) – VOUT) × IOUT(MAX) (1) Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance. On the WSON (DRV) package, the primary conduction path for heat is through the exposed power pad to the PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper PCB area . On the DSBGA (YKA) package, the primary conduction path for heat is through the four bumps to the PCB. |
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