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MSP430FG4619 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - Texas Instruments

๋ถ€ํ’ˆ๋ช… MSP430FG4619
์ƒ์„ธ๋‚ด์šฉ  MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
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MSP430FG4619 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - Texas Instruments

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RO/P(DAC12_x)
Max
0.3
AVCC
AVCC -0.3V
VOUT
Min
R Load
AVCC
CLoad =100pF
2
ILoad
DAC12
O/P(DAC12_x)
41
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508K โ€“ APRIL 2006 โ€“ REVISED MAY 2020
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Specifications
Copyright ยฉ 2006โ€“2020, Texas Instruments Incorporated
(1)
Data is valid after the offset calibration of the output amplifier.
5.35
12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VO
Output voltage range (see
Figure 5-29)(1)
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V, 3 V
0
0.005
V
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AVCC โ€“
0.05
AVCC
RLoad = 3 kโ„ฆ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
RLoad = 3 kโ„ฆ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
AVCC โ€“
0.13
AVCC
CL(DAC12)
Max DAC12 load
capacitance
2.2 V, 3 V
100
pF
IL(DAC12)
Max DAC12 load current
2.2 V
โ€“0.5
+0.5
mA
3 V
โ€“1.0
+1.0
RO/P(DAC12)
Output resistance (see
Figure 5-29)
RLoad = 3 kโ„ฆ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
2.2 V, 3 V
150
250
โ„ฆ
RLoad = 3 kโ„ฆ,
VO/P(DAC12) > AVCC โ€“ 0.3 V,
DAC12_xDAT = 0FFFh
150
250
RLoad = 3 kโ„ฆ,
0.3 V
โ‰ค VO/P(DAC12) โ‰ค AVCC โ€“ 0.3 V
1
4
Figure 5-29. DAC12_x Output Resistance Tests
(1)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC โ€“ VE(O)] / [3 ร— (1 + EG)].
(3)
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC โ€“ VE(O)] / (1 + EG).
(5)
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
5.36
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VeREF+
Reference input voltage
range
DAC12IR = 0(1) (2)
2.2 V, 3 V
AVCC/3
AVCC + 0.2
V
DAC12IR = 1(3) (4)
AVCC
AVCC + 0.2
Ri(VREF+),
(Ri(VeREF+)
Reference input resistance
DAC12_0 IR = DAC12_1 IR = 0
2.2 V, 3 V
20
M
โ„ฆ
DAC12_0 IR = 1, DAC12_1 IR = 0
40
48
56
k
โ„ฆ
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1
SREFx(5)
20
24
28


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