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MSP430FG4619 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 71 Page - Texas Instruments

๋ถ€ํ’ˆ๋ช… MSP430FG4619
์ƒ์„ธ๋‚ด์šฉ  MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
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MSP430FG4619 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 71 Page - Texas Instruments

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Bus
Keeper
EN
Direction
0: Input
1: Output
P 3SEL .x
1
0
P3DIR .x
P3IN .x
DVSS
DVSS
PadLogic
DVSS
D
EN
ModuleXIN
1
0
ModuleXOUT
P3OUT .x
Note: x = 0,1,2,3
P 3.0/UCB 0STE
P 3.1/UCB 0SIMO /UCB 0SDA
P 3.2/UCB 0SOMI /UCB 0SCL
P 3.3/UCB 0CLK
71
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508K โ€“ APRIL 2006 โ€“ REVISED MAY 2020
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Detailed Description
Copyright ยฉ 2006โ€“2020, Texas Instruments Incorporated
(1)
X = don't care
(2)
The pin direction is controlled by the USCI module.
(3)
If the I2C functionality is selected the output drives only the logical 0 to VSS level.
6.10.5 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
Table 6-15. Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR
SIGNALS(1)
P3DIR.x
P3SEL.x
P3.0/UCB0STE
0
P3.0 (I/O)
I: 0; O: 1
0
UCB0STE (2)
X
1
P3.1/UCB0SIMO/UCB0SDA
1
P3.1 (I/O)
I: 0; O: 1
0
UCB0SIMO/UCB0SDA (2) (3)
X
1
P3.2/UCB0SOMI/UCB0SCL
2
P3.2 (I/O)
I: 0; O: 1
0
UCB0SOMI/UCB0SCL (2) (3)
X
1
P3.3/UCB0CLK
3
P3.3 (I/O)
I: 0; O: 1
0
UCB0CLK (2)
X
1


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