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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MSP430FR6007 데이터시트(PDF) 80 Page - Texas Instruments |
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MSP430FR6007 데이터시트(HTML) 80 Page - Texas Instruments |
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80 / 179 page  80 MSP430FR6007, MSP430FR6005 SLASEV3 – MARCH 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR6007 MSP430FR6005 Detailed Description Copyright © 2020, Texas Instruments Incorporated 6.9 FRAM Controller A (FRCTL_A) The FRAM can be programmed through the JTAG port, SBW, the BSL, or in-system by the CPU. Features of the FRAM include: • Ultra-low-power ultra-fast-write nonvolatile memory • Byte and word access capability • Programmable wait state generation • Error correction coding (ECC) NOTE Wait States For MCLK frequencies > 8 MHz, wait states must be configured following the flow described in the "Wait State Control" section of the FRAM Controller A (FRCTRL_A) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide. For important software design information regarding FRAM including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses, see MSP430™ FRAM Technology – How To and Best Practices. 6.10 RAM The RAM is made up of three sectors: Sector 0 = 2KB, Sector 1 = 2KB, Sector 2 = 4KB (shared with LEA). Each sector can be individually powered down in LPM3 and LPM4 to save leakage. All data in the sector is lost when a sector is powered down. 6.11 Tiny RAM Tiny RAM is 22 bytes of RAM in addition to the complete RAM (see Table 6-45). This memory is always available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is powered down in LPM3 and LPM4. No memory is available in LPMx.5. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access. Features of the MPU include: • IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from outside the application; for example, through JTAG or by non-IP software). • Main memory partitioning is programmable up to three segments in steps of 1KB. • Access rights of each segment can be individually selected (main and information memory). • Access violation flags with interrupt capability for easy servicing of access violations. |
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