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AM49DL640AG 데이터시트(HTML) 4 Page - Advanced Micro Devices

부품명 AM49DL640AG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Download  65 Pages
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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AM49DL640AG 데이터시트(HTML) 4 Page - Advanced Micro Devices

 
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April 1, 2003
Am49DL640AG
3
PR E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V
SS ...11
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Word/Byte Configuration ........................................................ 12
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 3. Am29DL640G Sector Architecture ....................................14
Table 4. Bank Address ....................................................................17
Table 5. SecSi
 Sector Addresses ...............................................17
Sector/Sector Block Protection and Unprotection .................. 18
Table 6. Am29DL640G Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................18
Write Protect (WP#) ................................................................ 19
Table 7. WP#/ACC Modes ..............................................................19
Temporary Sector Unprotect .................................................. 19
Figure 1. Temporary Sector Unprotect Operation ...........................19
Figure 2. In-System Sector Protect/Unprotect Algorithms ..............20
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 21
Figure 3. SecSi Sector Protect Verify ..............................................22
Hardware Data Protection ...................................................... 22
Low V
CC Write Inhibit ........................................................... 22
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Flash Command Definitions . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 26
Byte/Word Program Command Sequence ............................. 27
Unlock Bypass Command Sequence .................................. 27
Figure 4. Program Operation ..........................................................28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 5. Erase Operation ...............................................................29
Flash Write Operation Status . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 6. Data# Polling Algorithm ...................................................31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 7. Toggle Bit Algorithm ........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 13. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 8. Maximum Negative Overshoot Waveform ...................... 35
Figure 9. Maximum Positive Overshoot Waveform ........................ 35
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 36
CMOS Compatible .................................................................. 36
Figure 10. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 37
Figure 11. Typical I
CC1 vs. Frequency ............................................ 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Test Setup .................................................................... 39
Figure 13. Input Waveforms and Measurement Levels ................. 39
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
pSRAM CE#s Timing .............................................................. 40
Figure 14. Timing Diagram for Alternating
Between pSRAM to Flash .............................................................. 40
Read-Only Operations ........................................................... 41
Figure 15. Read Operation Timings ............................................... 41
Hardware Reset (RESET#) .................................................... 42
Figure 16. Reset Timings ............................................................... 42
Word/Byte Configuration (CIOf) .............................................. 43
Figure 17. CIOf Timings for Read Operations ................................ 43
Figure 18. CIOf Timings for Write Operations ................................ 43
Erase and Program Operations .............................................. 44
Figure 19. Program Operation Timings .......................................... 45
Figure 20. Accelerated Program Timing Diagram .......................... 45
Figure 21. Chip/Sector Erase Operation Timings .......................... 46
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 47
Figure 23. Data# Polling Timings (During Embedded Algorithms) . 47
Figure 24. Toggle Bit Timings (During Embedded Algorithms) ...... 48
Figure 25. DQ2 vs. DQ6 ................................................................. 48
Temporary Sector Unprotect .................................................. 49
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 49
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 50
Alternate CE#f Controlled Erase and Program Operations .... 51
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings .......................................................................... 52
Power Up Time ....................................................................... 53
Read Cycle ............................................................................. 53
Figure 29. pSRAM Read Cycle—Address Controlled .................... 53
Read Cycle ............................................................................. 54
Figure 30. pSRAM Read Cycle ...................................................... 54
Write Cycle ............................................................................. 55
Figure 31. pSRAM Write Cycle—WE# Control .............................. 55
Figure 32. pSRAM Write Cycle—CE1#s Control ........................... 56
Figure 33. pSRAM Write Cycle—
UB#s and LB#s Control .................................................................. 57
Flash Erase And Programming Performance . . 58
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 58
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 58
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 58


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