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TLE9271QX 데이터시트(PDF) 86 Page - Infineon Technologies AG |
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TLE9271QX 데이터시트(HTML) 86 Page - Infineon Technologies AG |
86 / 126 page TLE9271QX Supervision Functions Datasheet 86 Rev.1.5 2019-09-27 13.3 VS Power ON Reset When powering up, the device detects the VS Power on Reset when VS > VPOR,r, and the SPI bit POR is set to indicate that all SPI registers are set to POR default settings. The Buck regulator starts up. The reset output is kept LOW and is only released when VCC1 has exceeded VRT1,r and after tRD1 has elapsed. If VS < VPOR,f, an internal reset is generated and the SBC is switched OFF. The SBC will restart in INIT mode when VS > VPOR,r rising. Timing behavior is shown in Figure 42. Figure 42 Ramp up / down example of Supply Voltage 13.4 Under Voltage VLIN When the supply voltage VLIN reaches the undervoltage threshold (VLIN,UVD) the SBC does the following actions: •The SPI bit VLIN_UV is set. No other error bits are set. The bit can be cleared once the condition is no longer present; • LIN is set to LIN Receive Only Mode. For additional information, please refer to Chapter 9.2.7. t VCC1 t VPOR,f RO t VS VPOR,r tRD1 VRT1,r VRTx,f t SBC Mode SBC OFF SBC OFF SBC INIT MODE Any SBC MODE SPI Command The reset threshold can be configured via SPI in SBC Normal Mode , default is VRT1 Re- start SBC Restart Mode is entered whenever the Reset is triggered |
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