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JN5189 데이터시트(PDF) 65 Page - NXP Semiconductors

부품명 JN5189
상세설명  IEEE 802.15.4 low power wireless MCU
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제조업체  NXP [NXP Semiconductors]
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JN5189 데이터시트(HTML) 65 Page - NXP Semiconductors

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JN5189
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Product data sheet
Rev. 1.2 — June 2020
65 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
14.8 PWM timing
14.9 DMIC timing
Fig 16. SPIFI interface timings
SPIFI_SCK
SPIFI data out
SPIFI data in
Tcy(clk)
tDS
tDH
tv(Q)
DATA VALID
DATA VALID
th(Q)
DATA VALID
DATA VALID
SPIFI_SSEL
tSS
tSH
Table 35.
PWM timing
VDDE = 1.9 V to 3.6 V; Tj =
−40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge;
simulated skew (over process, voltage and temperature) of any two PWM output signals; values guaranteed by design.
Symbol
Parameter
Min
Typ
Max
Unit
tSK
Output skew time
0
10
ns
Table 36.
DMIC timing
VDDE = 1.9 V to 3.6 V; Tj =
−40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge;
bypass bit = 0; based on simulated values and for 1.9 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tcy(SCK)
DMIC CLK frequency

2
MHz
Duty cycle
CL = 10 pF using 32MHz XTAL clock
source
48
52
%
tDS
Data set-up time
25

ns
tDH
Data hold time
1

ns


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