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BQ21062 데이터시트(PDF) 54 Page - Texas Instruments

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부품명 BQ21062
상세설명  BQ21062 I2C Controlled 1-Cell 500-mA Linear Battery Charger with Power Path, Load Switch, 10-nA Ship Mode, and Regulated System (PMID) Voltage
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10.2.1 Design Requirements
The design parameters for the following design example are shown in Table 10-1 below.
Table 10-1. Design Parameters
PARAMETER
VALUE
IN Supply Voltage
5 V
Battery Regulation Voltage
4.35V
LDO Output Voltage
LDO (1.8 V)
10.2.2 Detailed Design Procedure
10.2.2.1 Input (IN/PMID) Capacitors
Low ESR ceramic capacitors such as X7R or X5R is preferred for input decoupling capacitors and should be
places as close as possible to the supply and ground pins fo the IC. Due to the voltage derating of the capacitors
it is recommended at 25-V rated capacitors are used for IN and PMID pins which can normally operate at 5 V.
After derating the minimum capacitance must be higher than 1 µF.
10.2.2.2 VDD, LDO Input and Output Capacitors
A Low ESR ceramic capacitor such as X7R or X5R is recommended for the LDO decoupling capacitor. A 4.7-µF
capacitor is recommended for VDD output. For the LDO output a 2.2-µF capacitor is recommended. The
minimum supported capacitance after derating must be higher than 1 µF to ensure stability. The VINLS input
bypass capacitor value should match or exceed the LDO output capacitor value.
10.2.2.3 TS
A 10-KΩ NTC should be connected in parallel to a 10-kΩ biasing resistor connected to ground. The ground
connection of both the NTC and biasing resistor must be done as close as possible to the GND pin of the device
or kelvin connected to it to minimize any error in TS measurement due IR drops on the board ground lines.
If the system designer does not wish to use the TS function for charging control, a 5-kΩ resistor from TS to
ground must be connected.
10.2.2.4 Recommended Passive Components
Table 10-2. Recommended Passive Components
MIN
NOM
MAX
UNIT
CPMID
Capacitance in PMID pin
1(1)
22
47
µF
CLDO
LDO output capacitance
1
2.2
4.7
µF
CVDD
VDD output capacitance
1
2.2
4.7
µF
CBAT
BAT pin capacitance
1
µF
CIN
IN input bypass capacitance
1
4.7
10
µF
CINLS
VINLS input bypass capacitance
1
µF
CTS
Capacitance from TS pin to ground
0
0
1
nF
(1)
For PMID regulation loop stability, for better transient performance a minimum capacitance (after derating) of 10 µF is recommended.
BQ21062
SLUSE42 – JULY 2020
www.ti.com
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