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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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BQ77904 데이터시트(PDF) 23 Page - Texas Instruments |
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BQ77904 데이터시트(HTML) 23 Page - Texas Instruments |
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23 / 46 page  DISABLED (FET OFF) ENABLED ENABLED VSS VCTR1 VCTR2 VCTRDIS (min) CHG driver set by CTRC DSG driver set by CTRD VDD VCTRDIS (max) Figure 8-8. External Override of CHG and DSG Drivers 8.3.10 Configuring 3-S, 4-S, or 5-S Mode The BQ77904 supports 3-S and 4-S packs, while the BQ77905 supports 3-S, 4-S, and 5-S packs. To avoid accidentally detecting a UV fault on unused (shorted) cell inputs, the device must be configured for the specific cell count of the pack. This is set with the configuration pin, CCFG, which is mapped as in Table 8-5. The device periodically checks the CCFG status and takes tCCFG_DEG time to detect the pin status. Table 8-5. CCFG Configurations CCFG CONFIGURATION CONNECT TO < VCCFGL for tCCFG_DEG 3 cells AVSS Within VCCFGM for tCCFG_DEG 4 cells AVDD > VCCFGH for tCCFG_DEG 5 cells Floating The CCFG pin should be tied to the recommended net from Table 8-5. The device compares the CCFG input voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is for 5 S, leave the CCFG pin floating. The internal pin bias is approximately 30% of the AVDD voltage for the 5-S configuration. Note that the BQ77904 should not be configured in 5-S mode, as this results in a permanent UV fault. 8.3.11 Stacking Implementations Higher than 5-S cell packs may be supported by daisy-chaining multiple devices. Each device ensures OV, UV, OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions automatically disable the global CHG and/or DSG FET driver. Note that upper devices do not provide OCD1, OCD2, or SCD protections, as these are based on pack current. For the BQ77904 and BQ77905 devices used on the upper stack, the SRP and SRN pins should be shorted to prevent false detection. Table 8-6. Stacking Implementation Configurations CONFIGURATION CHG PIN CHGU PIN Bottom or single device Connect to CHG FET Leave unconnected Upper stack Leave unconnected Connect to CTRC of the lower device To configure higher-cell packs, follow this procedure: • Each device must have a connection on at least three lowest-cell input pins. • TI recommends to connect a higher-cell count to the upper devices (for example, for a 7-S configuration, connect four cells on the upper device and three cells on the bottom device). This provides a stronger CRTx signal to the bottom device. www.ti.com BQ77904, BQ77905 SLUSCM3K – APRIL 2020 – REVISED JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: BQ77904 BQ77905 |
유사한 부품 번호 - BQ77904_V04 |
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유사한 설명 - BQ77904_V04 |
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