Copyright © Future Technology Devices International Limited

12

FT602Q IC Datasheet

Version 1.4

Document No.: FT001389

Clearance No.: FTDI#519

For example, at idle, DATA[8] is logic”0”, which indicates USB IN channel 1 FIFO space is empty and able to

receive data . The external bus master will start a transfer cycle by asserting WR_N based on the channel

FIFO status. The first cycle after WR_N is asserted is the command phase, followed by the data phase when

RXF_N is asserted. At the command phase, the bus master will send the channel number which it intends to

transfer data with on DATA[7:0] and the Write command on BE[3:0]. BE[3:0] = ‘h1 indicates a master write.

There may also be a required turn-a-round for DATA[31:0] and BE[3:0] after the command phase and at the

end of data transaction.

Table 4.1 shows Multi-Channel FIFO mode command phase master write and channel address setting.

Command Phase

FT602 Command

BE[3:0]

Channel Address DATA[7:0]

Master Write

0001

8’h1=Channel 1

8’h2=Channel 2

8’h3=Channel 3

8’h4=Channel 4

All other values are reserved and shall be ignored

Table 4.1 Multi-Channel FIFO mode Command phase

Note: The channels can be configured by using the FT602 Chip Configuration utility.

The waveform below shows a FT602 master write transaction for 14 bytes at channel 1 with the bus master

terminating the transaction. There are turn-a-round cycles for DATA[15:8] after the command phase and at

the end of the data transaction. The BE[3:0] shows that the lower 2 bytes in D3 are valid at the last word

strobe in this transaction.

Figure 4.1 Multi-Channel FIFO mode master write transaction 1

NOTE: There is no turnaround phase for BE pins as these remain inputs when the FIFO is being written to by

the master.

The waveform below shows a FT602 master write transaction where the FIFO at channel 1 uses all data space

first, the RXF_N reasserts when the FIFO data space is not available after D3. There are turn-a-round cycles

for DATA[15:8] after the command phase and at the end of the data transaction. The BE[3:0] shows that the

transaction is all word aligned, all 4 bytes in D3 are valid at the last word strobe in this transaction.