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TDA9965 데이터시트(PDF) 8 Page - NXP Semiconductors |
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TDA9965 데이터시트(HTML) 8 Page - NXP Semiconductors |
8 / 22 page 2004 Jul 05 8 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 tW(SHD) SHD pulse width Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 9 −− ns code fco(CTH) 0000 − 8 − ns 0001 − 13 − ns 0010 − 17 − ns 0100 − 23 − ns 1000 − 33 − ns 1111 − 51 − ns th(IN-SHP) CTH input hold time compared to control pulse SHP see Fig.5 − 3 − ns th(IN-SHD) CTH input hold time compared to control pulse SHD see Fig.5 − 3 − ns Programmable Gain Amplifier (PGA) output: pin PGAOUT VPGAOUT(p-p) PGA output amplifier dynamic voltage level (peak-to-peak value) − 2000 − mV VPGAOUT(b) PGA output amplifier black level voltage code C(CLP) =0 − 1.475 − V ZPGAOUT PGA output amplifier output impedance fpix at 10 kHz for minimum and maximum values − 5 −Ω IPGAOUT PGA output current drive static −− 1mA GPGA(min) minimum gain of PGA circuit code GPGA =0 − 0 − dB GPGA(max) maximum gain of PGA circuit code GPGA ≥767 − 36 − dB Analog-to-Digital Converter (ADC) fpix(max) maximum pixel frequency 30 −− MHz tW(CLKADC)H CLKADC pulse width HIGH Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 12 −− ns tW(CLKADC)L CLKADC pulse width LOW Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128 12 −− ns SRCLKADC CLKADC input slew rate rising and falling edges; 10% to 90% 0.5 −− V/ns Vi(ADCIN)(p-p) ADC input voltage (peak-to-peak value) with internal regulator − 2 − V Ii(ADCIN) ADC input current −2 − +120 µA VRB ADC reference voltage bottom − 1.30 − V VRT ADC reference voltage top − 3.65 − V SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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