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TC59LM806CFT-55 데이터시트(PDF) 5 Page - Toshiba Semiconductor

부품명 TC59LM806CFT-55
상세설명  4,194,304 / 8,388,608-WORDS x 4 BANKS x 16 / 8-BITS Network FCRAM
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC59LM806CFT-55 데이터시트(HTML) 5 Page - Toshiba Semiconductor

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TC59LM814/06CFT-50,-55,-60
2002-08-19
5/38
Note:
(1)
All voltages referenced to VSS, VSSQ.
(2)
VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3)
Overshoot limit: VIH (max) = VDDQ + 0.9 V with a pulse width ≤ 5 ns.
(4)
Undershoot limit: VIL (min) = −0.9 V with a pulse width ≤ 5 ns.
(5)
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6)
VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7)
VID is magnitude of the difference between CLK input level and CLK input level.
(8)
The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9)
VISO means {VICK (CLK) + VICK ( CLK )} /2
(10)
Refer to the figure below.
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC)
± 0.04 V.
CAPACITANCE (VDD
,,,, VDDQ ==== 2.5 V, f ==== 1 MHz, Ta ==== 25°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
CIN
Input pin Capacitance
2.5
4.0
pF
CINC
Clock pin (CLK, CLK ) Capacitance
2.5
4.0
pF
CI/O
I/O pin (DQ, DQS) Capacitance
4.0
6.0
pF
CNC
1
NC
1
pin Capacitance
1.5
pF
CNC
2
NC
2
pin Capacitance
4.0
6.0
pF
Note: These parameters are periodically sampled and not 100% tested.
The NC
2
pins have additional capacitance for adjustment of the adjacent pin capacitance.
The NC
2
pins have Power and Ground clamp.
VISO (min)
VISO (max)
VICK
VICK
Vx
Vx
Vx
Vx
Vx
VICK
VICK
CLK
CLK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
VID (AC)


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