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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LTC3246 데이터시트(HTML) 14 Page - Analog Devices |
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LTC3246 데이터시트(HTML) 14 Page - Analog Devices |
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LTC3246 14 3246fa For more information www.linear.com/LTC3246 APPLICATIONS INFORMATION Reset Generation (RSTI input, RST output) The LTC3246 pulls the RST open-drain output low when- ever RSTI is below threshold (typically 1.2V) or VOUT is greater than the overvoltage threshold or less than the undervoltage threshold. RST remains asserted low for a reset timeout period (tRST) once RSTI goes above the threshold and VOUTisinregulation(withintheovervoltage and undervoltage thresholds). RST de-asserts by going high impedance at the end of the reset timeout period. The reset timeout can be configured to use an internal timer without external components or an adjustable timer programmed by connecting an external capacitor from the RT pin to GND. Glitch filtering ensures reliable reset operation without false triggering. During initial power up, the RST output asserts low while VIN is below the VIN undervoltage lockout threshold. The state of VOUT and RSTI have no effect on RST while VIN is below the undervoltage lockout threshold. The reset timeout period cannot start until VIN exceeds the under- voltage lockout threshold. VOUT Undervoltage/Overvoltage Reset A built-in VOUTsupplymonitorensurestheVOUTisinregu- lation before RST is allowed to go high impedance. The monitor detects both overvoltage and undervoltage faults. If VOUT is greater than the overvoltage threshold or less than the undervoltage threshold, the part registers a fault and pulls RST low. The fault condition is removed when VOUTiswithintheovervoltageandundervoltagethresholds. Load transients within the operating range of the part will not registering as a fault by design. Selecting the Reset Timing Capacitor The reset timeout period can be set to a fixed internal timer or programmed with a capacitor in order to accom- modate a variety of applications. Connecting a capacitor, CRT, between the RT pin and GND sets the reset timeout period, tRST. Figure 4 shows the desired reset timeout period as a function of the value of the timer capacitor. Leaving RT open without external capacitor generates a reset timeout of approximately 0.5ms. Shorting RT to BIAS generates a reset timeout of approximately 0.2s. 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 10000 3246 F04 CRT (nF) Figure4. Reset Timeout Period vs CRT Capacitance RST Output Characteristics RST is an open-drain pin and, thus, requires an external pull-up resistor to a logic supply. RST may be pulled up to any valid logic level (such as VOUT) providing the voltage limits of the pin are observed (See Absolute Maximum Ratings section). Watchdog Timer (WDI input, RST output) The LTC3246 includes a windowed watchdog function that can continuously monitor the application’s logic or microprocessorandissueautomaticresetstoaidrecovery from unintended lockups or crashes. With the RSTI input held above threshold, the application must periodically toggle the logic state of the watchdog input (WDI pin) in order to clear the watchdog timer. Specifically, successive falling edges on the WDI pin must be spaced by more than the watchdog lower boundary but less than the watchdog upper boundary. As long as this condition holds, RST remains high impedance. If a falling edge arrives before the watchdog lower bound- ary, or if the watchdog timer reaches the upper bound- ary without seeing a falling edge on WDI, the watchdog timer immediately enters its reset state and asserts RST |
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