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LTC3246 ๋ฐ์ดํฐ์ํธ(HTML) 15 Page - Analog Devices |
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LTC3246 ๋ฐ์ดํฐ์ํธ(HTML) 15 Page - Analog Devices |
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LTC3246 15 3246fa For more information www.linear.com/LTC3246 APPLICATIONS INFORMATION low for the reset timeout period. Once the reset timeout completes, RST is released to go high and the watchdog timer starts again. Duringpower-up,thewatchdogtimerremainsclearedwhile RST is asserted low. As soon as the reset timer times out, RST goes high and the watchdog timer is started. Setting the Watchdog Timeout Period The watchdog upper boundary (tWDU) and lower bound- ary (tWDL) are not observable outside the part; only the watchdog timeout period (tWDR) of the part is observable via the RST pin. The watchdog upper boundary (tWDU) occurs one watchdog clock cycle before the watchdog timeout period (tWDR). The internal watchdog timeout period consists of 8193 clock cycles, so the internal watchdog upper boundary time is essentially the same as the internal watchdog timeout period. Conversely, the external watchdog timeout period consists of only 129 clock cycles, so the external watchdog upper boundary should be more accurately calculated as: tWDU(EXT) = tWDR(EXT) โข 128 129 The external watchdog lower boundary (tWDL(EXT)) oc- curs five clock cycles into the watchdog timeout period (tWDR(EXT)). Thus the external watchdog lower boundary can be calculated from the external watchdog timeout period as: tWDL EXT = tWDR(EXT) โข 5 129 The internal watchdog lower boundary can be calcu- lated from the internal watchdog timeout period by the following: tWDL(INT) = tWDR(INT) 32 The watchdog upper boundary is adjustable and can be optimized for software execution. The watchdog upper boundary is adjusted by connecting a capacitor, CWT, between the WT and GND pins. Figure 5 shows the approximate external watchdog timeout period as a function of the watchdog capacitor. Shorting WT to BIAS sets an upper and lower watchdog timeout period of about 50ms and 1.6s respectively. Figure5. External Watchdog Timeout Period vs CWT Capacitance 0.001 0.01 0.1 1 10 100 1000 1 10 100 1000 10000 100000 3246 F05 CWT (nF) Layout Considerations Due to the high switching frequency and transient cur- rents produced by the LTC3246, careful board layout is necessary for optimal performance. A true ground plane and short connections to all capacitors will optimize performance, reduce noise and ensure proper regulation over all conditions. WhenusingtheLTC3246withanexternalresistordividerit is important to minimize any stray capacitance to the ADJ (OUTS/ADJ pin) node. Stray capacitance from ADJ to C+ or Cโ can degrade performance significantly and should be minimized and/or shielded if necessary. Minimize stray capacitance from WT and RT to C+ and Cโ when using external timing capacitors to minimize timing variation. Thermal Management/Thermal Shutdown Theon-chippowerdissipationintheLTC3246willcausethe junction to ambient temperature to rise at rate of typically 40ยฐC/W in still air with a good thermal connection to the PC board. Connecting the die pad (Pin 17) with multiple vias to a large gro und plane under the device can reduce the thermal resistance of the package and PC board con- |
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